| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 95 === The thesis presents an Ultra Wideband (UWB) receiver front end, frequency synthesizer and V band injection locked frequency divider, which are implemented in TSMC 0.18-μm and 0.13-μm CMOS technologies, respectively.
The functional block of Ultra wide band (UWB) receiver front end includes a low noise amplifier (LNA) and a mixer. The low noise amplifier employs the RC shunt feedback technique for broadening the bandwidth. Besides, an inductor is used as an interstage matching at the cascode LNA which efficiently improve the flatness of the cascode LNA. The RC shunt feedback is applied to the gm stage of mixer for input impedance matching of reveiver. The experimental results of the receiver are a conversion gain of 19.29 ~ 17.12 dB (Single-ended), an input return loss better than 6.7 dB, a noise figure of 5.25 ~ 6.89 dB (DSB) at 100 MHz IF frequency, 1-dB compression point of -24 ~ -28 dBm, an input third order intercept point of -7 ~ -11 dBm, an LO-IF isolation of -44 ~ -57 dB, an LO-RF isolation of -52.5 ~ -77 dB, an RF-IF isolation of -19.6 ~ -59 dB. The total power consumption is 29.1 mW.
The circuit block of ultra wideband (UWB) frequency synthesizer includes a quadrature voltage control oscillator (QVCO), a current mode logic (CML) divider, a true single phase clock (TSPC) divider, a frequency selector, a single sideband mixer (SSB Mixer), a phase frequency detector (PFD), a charge pump and a loop filter. The experimental results show that the designed sysnthesizer generates six bands for the local signals in UWB transmitter system. In the VCO design, the binary weighted band switching capacitor is used to calibrate the frequency drifting under process variations. Beside, a useful formula is proposed to choose the value of varactor and band switching capacitor. In frequency selector deisgn, the proposed dummy transistor is added to improve isolation. The measured close loop phase noise is -103.51 dBc/Hz at 1 MHz offset and -80.53 dBc/Hz at 10 kHz offset in 8.448 GHz band. The settling time of this loop is about 10 μs. The switching time between two sub-bands is small then 1 ns. The sideband suppression is low as -37.75 dBc in the 6336 MHz band. The total power consumption of the synthesizer is 93.4 mW.
Two injection locked frequency dividers was investigated in this study. In the first injection locked frequency divider, the obtained locking range is 180 MHz with injection power of 5 dBm at Vtune of 1.8V. The total loacking range of divider is from 58.02 ~ 65.99 GHz which is correspondent to a locking range of 7.97 GHz while varying Vtune from 0 V to 1.8 V. The power consumption of core circuit and buffer amplifier is 1.395 mW and 3.48 mW, respectively. The second topology of frequency divider is the improvement version with respect to the first one. The difference between these two dividers is the second topology of frequency divider without using preamplifier, instead of the proposed transformer direct injection method to improve injection efficiency and locking range. The second proposed ILFD achieved the locking range of 1.75 GHz at the injection power of 5 dBm and Vtune of 1.8 V. The total locking range of the divider is from 56.5 to 66.4 GHz which is correspondent to a locking range of 9.9 GHz while varying Vtune from 0 V to 1.8 V. The power consumption of core circuit and buffer amplifier is 3 mW and 3.85 mW, respectively.
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