| Summary: | 碩士 === 國立交通大學 === 電機學院微電子奈米科技產業專班 === 95 === In this thesis, first, we used a post-anneal procedure with oxygen ambient after the deposition of gate oxide. Poly-Si TFTs with such a post-anneal procedure have enhanced electrical characteristics and much improved reliability. In addition, we deposited a buffer amorphous Si (a-Si) layer under both low temperature and pressure before the deposition of the channel. Si layers grown under this condition would have higher oxygen concentration, and this would suppress the nucleation mechanism under solid-phase crystallization (SPC). With the buffer Si layer, the bi-layer Si, with a-Si layer beneath the poly-Si channel after the SPC process, would have larger grain size and lead to enhanced performance. Measurements revealed that the devices’ electrical characteristics are improved not only in field effect mobility and gate-induced-drain leakage (GIDL) current, but also in driving current and
subthreshold swing. Moreover, the ability of immunity against hot-carrier injection and device uniformity are improved.
Then, we studied the degradation mechanisms of negative bias temperature instablity (NBTI) and positive bias temperature instability (PBTI) in p- and n-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs), respectively. As the stress gate voltage increases, the absolute values of threshold voltages shift (|ΔVth|) increase under NBTI and PBTI stress. When the stress temperature is raised, the |ΔVth| increases under NBTI stress but almost unchanged under PBTI stress, indicating that the degradation mechanisms of NBTI and PBTI are different. Furthermore, the field-effect mobility is rarely changed under NBTI stress; however, it increases under PBTI stress. From the experimental results, we demonstrated that the NBTI degradation can be explained by the diffusion-controlled electrochemical reactions, while the PBTI degradation is caused by charge trapping in the gate dielectric.
Finally, we investigated the impact of dynamic NBTI in p-channel LTPS TFTs. In conventional NBTI studies, static gate bias is used to determine the lifetime of p-channel LTPS TFTs. However, DNBTI in p-MOSFETs showed that the lifetime was much longer than that derived from static NBTI stress because of the passivation effect. We found that LTPS p-TFTs have passivation effect under positive gate bias during a stress-passivation-stress process. As a result, we would underdetermine the true lifetime of LTPS p-TFTs when we use static NBTS to derive it. Therefore, it is necessary to use DNBTS to simulate the bias condition of their really applications.
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