On Resource-Efficient Low-Power VLSI Signal Processing Design

• Main Authors: Hsueh-Chih Yang, 楊學之
• Other Authors: Lan-Rong Dung
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/54530879316835048658

博士 === 國立交通大學 === 電機與控制工程系所 === 95 === The primary design objective of computing and communication systems has been targeting on the following performance metrics: the speed of signal processing, the rate of communications, and the optimization of quality of service. For portable embedded computing systems and wireless systems deployed on a large scale and untethered to power sources, practical considerations dictate a different design regime, one that should be dominated by energy and cost constraints. Batteries are serving as a dedicated energy resource. The requirement of portability places severe restrictions on size and weight, which in turn limits the amount of energy that is continuously available to maintain system operability. For these reasons, a fundamental shift in design paradigm is necessary: from focusing on performance to focusing on constraints, from maximizing data rate to maximizing resource efficiency. This dissertation illuminates the impact of resource constraints on the design methodologies of VLSI signal processing and communication applications, proposes several design methodologies in the resource-constrained low-power high-level synthesis (HLS), the limited-resource folding techniques, and the power efficient turbo decoder, and tries to stimulate interests in the VLSI signal processing in reformulating and revisiting classic VLSI signal processing problems under new constraints and exploring the role of signal processing in exciting new applications. Based on the proposed techniques, we have designed and implemented two power-efficient chips, a pulse shaping FIR filter for WCDMA and a limited-resource DWT processor.