A 12-bit 500-MSamples/s Current-Steering CMOS D/A Converter

• Main Authors: Tsung-Yen Tsai, 蔡宗諺
• Other Authors: Chung-Chih Hung
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/94140123580238255874

碩士 === 國立交通大學 === 電信工程系所 === 95 === Digital-To-Analog converters are essential components of modern applications, such as digital signal synthesis, video signal processing, and both wired and wireless transmitters.For data converters used in communications applications, the integral nonlinearity (INL) and differential nonlinearity (DNL) are not sufficient to characterize the performance. It is more convenient to characterize the performance in the frequency domain using measures as the spurious-free dynamic range (SFDR). The major target specification for SFDR of this paper, a 12-bit 500-MSample/s D/A converter, is 60 dB for signal frequencies up to 170 MHz. An additional design goal was to derive maximum benefit from this relatively advanced technology. This architecture is divided into a coarse sub-DAC and a binary-weighted fine sub-DAC. The differential switches of current sources are controlled by deglitch latch. The routing complexity and parasitic capacitance have to be considered for speed and signal synchronization. A 12-bit 500-MSample/s current-steering D/A converter integrated in a TSMC 0.18μm CMOS technology is presented. It is based on a current steering doubly segmented 8 + 4 architectureand requires no trimming, no calibration, or dynamic averaging. The increased switching noise associated with a high degree of segmentation has been reduced by a new latch. The measure resultant shows that with the signal frequency of 34.33 MHz at the update rate of 100 MHz, the SFDR is 32 dB. The differential nonlinearity and integral nonlinearity are below 3.3 and 5.4 least significant bits (LSB’s), respectively. The converter consumers a total power of 128 mW and it’s active area is 1.615 mm2.