The Design and Implementation of Low Power Third-Order Continuout-Time Sigma-Delta Modulator

• Main Authors: Cheng-Han Lin, 林政翰
• Other Authors: Chung-Chih Hung
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/35941579954151132347

碩士 === 國立交通大學 === 電信工程系所 === 95 === Along with rapid growth of battery-powered portable devices, such as laptop, cellular phones, and MP3 player, system on a chip (SOC) is an important issue to help devices become smaller and lighter. Moreover, batteries almost dominate portable devices’ sizes and weight. Therefore, reducing the power dissipation in chip is desirable so as reduce the number of battery cells and extend the battery lifetime as much as possible. Furthermore, the raising complexity on a chip results in an increase of power density, which leads to even higher demand for power reduction techniques. In today’s device application, digital circuits dominate the whole chip function. However, analog-to-digital converter (ADC) is also indispensable. Under these conditions, sigma-delta (ΣΔ) ADCs are very suitable for the application because they can achieve high accuracy for narrow band signals with few analog components and insensitivity to process and component variation. Typically, there are two kinds of ΣΔ ADCs. The first one is discrete-time (DT) ΣΔ ADC and another is continuous-time (CT) ΣΔ ADC. The DT ΣΔ ADC also called the switched-capacitor (SC) ΣΔ ADC because of using switched capacitors. Generally, in order to charge and discharge the capacitors in one clock time, the specification of an OPAMP , such as gain-bandwidth, slew rate and settling time, will be increased. But for CT ΣΔ ADC, it doesn’t need to process signals within a clock time, so the requirement of integrator will be reduced. This results in further power decreasing. In order to combine the advantages of the CT ΣΔ ADC system with low-frequency low-power applications, this research focuses on ultra low power audio CT ΣΔ ADC. The power consumption and area will be reduced compared with DT ΣΔ ADC. The chip has been fabricated by TSMC 0.18-um CMOS process.