A Study of Thin-Film Transistors with Poly-Si Nanowire Channels Fabricated by LTPS Technology

碩士 === 國立交通大學 === 電子工程系所 === 95 === In this thesis, two low-temperature poly silicon (LTPS) technologies are adopted to fabricate TFTs with poly-Si nanowire (NW) channels. One is solid phase crystallization (SPC), where gate-induced drain leakage (GIDL) is found to be the most dominant leakage mecha...

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Bibliographic Details
Main Authors: Yu-Fong Huang, 黃育峯
Other Authors: Horng-Chih Lin
Format: Others
Language:en_US
Published: 2007
Online Access:http://ndltd.ncl.edu.tw/handle/28933267786281162001
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Summary:碩士 === 國立交通大學 === 電子工程系所 === 95 === In this thesis, two low-temperature poly silicon (LTPS) technologies are adopted to fabricate TFTs with poly-Si nanowire (NW) channels. One is solid phase crystallization (SPC), where gate-induced drain leakage (GIDL) is found to be the most dominant leakage mechanism due to the unique layout feature in the proposed NW-TFTs. By introducing an additional deep ion implantation (I/I), the undesirable GIDL mechanism can be suppressed effectively. Both activation energy extraction and electric field strength simulation are also investigated for further discussion. The other is metal-induced lateral crystallization (MILC). Compared with SPC device, the performance of the MILC device is dramatically enhanced owing to the improvement of the film crystallinity. Besides, the impacts of seeding window arrangement and annealing temperature are also explored in this study.