The Design of a 3.1 ~ 10.6 GHz CMOS Direct-Conversion Receiver Front-End for UWB Applications

碩士 === 國立交通大學 === 電子工程系所 === 95 === As the increasing demands for low-power and high data-rate wireless communication, conventional wireless local area network of IEEE 802.11 a/b/g has found it difficult to suffice these requirements. In this thesis, the design methodology and implementation of a 3....

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Main Authors: Yi-Kai, Lo, 羅怡凱
Other Authors: Chung-Yu Wu
Format: Others
Language:en_US
Published: 2006
Online Access:http://ndltd.ncl.edu.tw/handle/69474282197457527021
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spelling ndltd-TW-095NCTU54280402016-05-25T04:13:41Z http://ndltd.ncl.edu.tw/handle/69474282197457527021 The Design of a 3.1 ~ 10.6 GHz CMOS Direct-Conversion Receiver Front-End for UWB Applications 應用於3.1~10.6GHz超寬頻射頻前端接收器 Yi-Kai, Lo 羅怡凱 碩士 國立交通大學 電子工程系所 95 As the increasing demands for low-power and high data-rate wireless communication, conventional wireless local area network of IEEE 802.11 a/b/g has found it difficult to suffice these requirements. In this thesis, the design methodology and implementation of a 3.1~10.6 GHz direct-conversion receiver for UWB application are presented according to the recently published IEEE 802.15.3a specification. The proposed direct-conversion receiver are composed of a new wideband low-noise amplifier (WLNA) used to receive 3.1~10.6 GHz signal simultaneously and a carrier generator to generate required 14-band carriers, and I/Q down-conversion mixers with output buffers for correct down-conversion of input signals and measurement consideration. Based on the simulation and measurement results, the proposed receiver receives signals of 3.1~5.4 GHz as a result of the oscillating frequency drift of VCO in the carrier generator. The measurement results present a overall noise figure (NF) of around 6.5~7dB, gain of 6.9~10.7 dB, input-referred 1-dB compression point (P1dB)of -16~-17.8 dBm, input third-order intercept point (IIP3) of -5~-2.5 dBm, out-of-band P1dB of -14~-18 dBm, and out-of-band IIP2 from second-order modulation of 4~5.8 dBm. It consumes 94 mW under 1.2-V power supply for WLNA and down-conversion mixers and 1.6-V for the carrier generator. Besides, a discussion about the malfunction and reasons of extraordinary high power consumption of the receiver is made; furthermore, a modification and revised-simulation of the receiver are proposed and done for further verification. In the light of revised-simulation results, the proposed receiver is confirmed to be suitable for low-power and high data-rate wireless communication systems. Future research will be conducted to implement a thorough transceiver for UWB applications. Chung-Yu Wu 吳重雨 2006 學位論文 ; thesis 139 en_US
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description 碩士 === 國立交通大學 === 電子工程系所 === 95 === As the increasing demands for low-power and high data-rate wireless communication, conventional wireless local area network of IEEE 802.11 a/b/g has found it difficult to suffice these requirements. In this thesis, the design methodology and implementation of a 3.1~10.6 GHz direct-conversion receiver for UWB application are presented according to the recently published IEEE 802.15.3a specification. The proposed direct-conversion receiver are composed of a new wideband low-noise amplifier (WLNA) used to receive 3.1~10.6 GHz signal simultaneously and a carrier generator to generate required 14-band carriers, and I/Q down-conversion mixers with output buffers for correct down-conversion of input signals and measurement consideration. Based on the simulation and measurement results, the proposed receiver receives signals of 3.1~5.4 GHz as a result of the oscillating frequency drift of VCO in the carrier generator. The measurement results present a overall noise figure (NF) of around 6.5~7dB, gain of 6.9~10.7 dB, input-referred 1-dB compression point (P1dB)of -16~-17.8 dBm, input third-order intercept point (IIP3) of -5~-2.5 dBm, out-of-band P1dB of -14~-18 dBm, and out-of-band IIP2 from second-order modulation of 4~5.8 dBm. It consumes 94 mW under 1.2-V power supply for WLNA and down-conversion mixers and 1.6-V for the carrier generator. Besides, a discussion about the malfunction and reasons of extraordinary high power consumption of the receiver is made; furthermore, a modification and revised-simulation of the receiver are proposed and done for further verification. In the light of revised-simulation results, the proposed receiver is confirmed to be suitable for low-power and high data-rate wireless communication systems. Future research will be conducted to implement a thorough transceiver for UWB applications.
author2 Chung-Yu Wu
author_facet Chung-Yu Wu
Yi-Kai, Lo
羅怡凱
author Yi-Kai, Lo
羅怡凱
spellingShingle Yi-Kai, Lo
羅怡凱
The Design of a 3.1 ~ 10.6 GHz CMOS Direct-Conversion Receiver Front-End for UWB Applications
author_sort Yi-Kai, Lo
title The Design of a 3.1 ~ 10.6 GHz CMOS Direct-Conversion Receiver Front-End for UWB Applications
title_short The Design of a 3.1 ~ 10.6 GHz CMOS Direct-Conversion Receiver Front-End for UWB Applications
title_full The Design of a 3.1 ~ 10.6 GHz CMOS Direct-Conversion Receiver Front-End for UWB Applications
title_fullStr The Design of a 3.1 ~ 10.6 GHz CMOS Direct-Conversion Receiver Front-End for UWB Applications
title_full_unstemmed The Design of a 3.1 ~ 10.6 GHz CMOS Direct-Conversion Receiver Front-End for UWB Applications
title_sort design of a 3.1 ~ 10.6 ghz cmos direct-conversion receiver front-end for uwb applications
publishDate 2006
url http://ndltd.ncl.edu.tw/handle/69474282197457527021
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