| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 95 === The proliferation of portable and mobile multimedia devices powered by batteries demands compact and low-power digital signal processors. This thesis presents an ultra lightweight DSP engine, which performs multiplier-less DSP arithmetic. The architecture is highly scalable for various performance requirements. Moreover, an integrated complexity-aware code generator is proposed, where various algorithmic and numerical optimizations are implemented. In our simulations, the proposed DSP engine with the integrated code generator needs only 1.4 operations/tap for FIR filtering, which can achieve comparable quality of MAC-based ones (i.e. 1 operation/tap), and the performance can be converted into 80%~90% computing time savings and 13%~14% energy reductions from MAC-based DSP engines in the TSMC 0.13μm CMOS technology. Finally, the complete DSP core has been designed with an AMBA AHB-compliant interface. The cell-based implementation in the TSMC 0.13μm CMOS technology operates at 400MHz (600MHz maximum) and consumes 22mW average power for typical FIR filtering. The core size is 0.6×0.6mm2 including 256 bytes memory.
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