A Capacitor-Free CMOS Low Dropout Linear Voltage Regulator

• Main Authors: Nan-Hsiung Tseng, 曾南雄
• Other Authors: Ke-Horng Chen
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/50122503490455813142

碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 95 === In the recent years, developing of low power circuits to extend battery life has become a critical research topic due to explosion growing of portable electric devices. In order to make products smaller and thinner, this is a necessary trend to integrate the circuit and reduce the external component. A power management system usually contains serval LDO regulators and switching regulators.The conventional LDO voltage regulator requires a very large output capacitor in the single microfarad range.Large microfarad capacitors can not easy integrated in IC, and take over a large area of PCB, consuming cost. The target of this paper is to design a low dropout linear voltage regulator without external capcitor. This LDO is based on three stage amplifiers design, and also consider the stability, resolution, transient response and other performances. The design of specification is shown is the following: The maxmium load current is 100mA. The input voltage is ranged from1.5V to 4.5V. The output voltage is 1.3V. The dropout voltage is 200mV. The quiescent current is consuming only 46uA containing the bandgap reference. This LDO is fabricated by TSMC 0.35um 2P4M process. Experimental results show that the proposed capacitor-free LDO voltage regulator is achieved the expected specification of stability and transient response.Thus, the proposed capacitor-free LDO voltage regulator is suitable for SoC solution.