| Summary: | 碩士 === 國立交通大學 === 電機學院碩士在職專班電子與光電組 === 95 === A 6-bit 2-GSample/s flash A/D converter with wide bandwidth and low power for ultra-wideband (UWB) application is demonstrated in CMOS technology. A low-power high-speed architecture by combining the cascade resistive averaging, interpolation, wideband sample-and-hold and digital error correction technique is proposed. The principle of averaging, interpolation, wideband sample-and- hold technique and digital error correction is analyzed and discussed in detail. Use the averaging, can reduce power in preamplifiers. Use the interpolation can halve the number of preamplifiers and halve input capacitance. Use the sample-and-hold can improve dynamic performance. Use the digital error correction to can eliminate the power of 2N-1 pipeline latches. With the combining techniques, a 6-bits flash A/D converter achieves effective 5.05 bits for input frequencies up to 976MHz at 2-GSample/s. The results show peak differential-nonlinearity (DNL) and integral-nonlinearity (INL) is less than 0.1LSB and 0.14LSB. The signal-to-noise and distortion ratio (SNDR) at 7.81MHz is 37.51dB and the spurious-free dynamic range (SFDR) at 7.81MHz is 48.94dB. Near Nyquiest input frequencies, SNDR and SFDR maintain above 32.2 and 33.68dB respectively. This flash A/D converter consumes 117mW from 1.2V power supply at 2-GSample/s, and a figure of merit (FOM) is only 1.8pJ.
The flash A/D converter is implemented in UMC 0.13μm 1P8M CMOS technology and has been packaged in SPIL QFN32 which is mounted on PCB board in favor of measurement. The measurement of the SNDR is 27.97dB under 2GHz sampling rate and 2.00MHz input frequency. The effective number of bits (ENOB) is calculated equal to 4.3 bits. The measured DNL and INL are +1.56/-1.00 LSB and +1.91/-1.85 LSB.
|
|---|
