The Design and Implementation of NAND-Flash-Based Paging Device

• Main Authors: Ni-Feng Chang, 張倪逢
• Other Authors: Jing Chen
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/05771588895927451201

碩士 === 國立成功大學 === 電腦與通信工程研究所 === 95 === NAND flash memory comes with features such as non-volatile, small physical size, low-power consumption, good shock-resistance etc. such that system designers tend to use NAND flash memory as the primary storage when designing mobile devices. However, the characteristics of out-of-place update, wear-leveling, and block-erasing make it very different from a hard disk. In an operating system with virtual memory, these characteristics become challenging issues when using NAND flash memory as paging device. This thesis presents a study in using NAND flash memory as the paging device in virtual memory management. An investigation on FTL (Flash Translation Layer), which is a common approach to encapsulate the characteristics of NAND flash memory, and the interaction between virtual memory management subsystem and paging device is undertaken. We propose a Swap FTL to manage NAND-Flash-based paging device. In addition to the functions which are commonly supported by FTL such as logical-physical address mapping, in-place update emulation, erase address management, Swap FTL provides a feature to avoid unnecessary living-copies caused by the out-of-place-update characteristic of NAND Flash. To support this feature, the kernel needs merely to implement an invalidation mechanism. To demonstrate the functionality of Swap FTL, a demo version is implemented in the MTD subsystem of Linux operating system. Its performance is evaluated by feeding a trace of paging addresses logged during some real-world operations. The results show that our approach works effectively and reduces the number of read, write, erase, and living-copies. Furthermore, the erase operations are evenly distributed to the blocks of NAND flash memory.