Implementation of High-Linearity, Low-Voltage CMOS Mixer and the Novel Doubler, Couplers MMIC

• Main Authors: Hua-yueh Chiu, 邱樺岳
• Other Authors: Yeong-Her Wang
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/97893051048244571238

碩士 === 國立成功大學 === 光電科學與工程研究所 === 95 === This thesis presents the implementation of high-linearity, low-voltage CMOS Mixer at 5.8 GHz in TSMC standard 0.18um CMOS process. A novel frequency doubler and a miniaturized broadband hybrid ring by using WIN and Transcom InGaAs PHEMT process, respectively, have been demonstrated. Final, a 3-dB quadrature coupler using broadside-coupled coplanar waveguides at 2.4 GHz in PCB is realized. First, a parallel LC-tank structure is added into Gilbert mixer for low operation voltage purpose. In RF stage, a cross-connect configuration with four pMOSs to replace the traditional nMOSs connection is proposed not only to reduce the noise figure but also to increase linearity. It exhibits a conversion gain of -13dB, IIP3 of 10.5 dB. Second, we design the single balanced frequency doubler with input Marchand balun. Due to the anti-phase relationships of the diodes, the odd harmonics can be suppressed. Using Marchand balun to replace hybrid circuits can reduce die size. It exhibits a conversion gain of -11.2±1dB, fundamental suppression of 11±1dBc and three-order suppression of 25±10dBc from 9 GHz to 14.5 GHz at 13 dBm input power. Third, a novel construction hybrid ring used 1/4λ Lange coupler and CPWG for reducing size and extending bandwidth. Final, a single-layer 3-dB quadrature coupler using broadside- coupled coplanar waveguides has been designed and analyzed. The proposed method enabled the recently published couplers with a broadside-coupled structure to be easily designed on a single-layer printed circuit without using a multi-layer substrate and an external metallic box.