Implementation of High-Linearity, Low-Voltage CMOS Mixer and the Novel Doubler, Couplers MMIC
碩士 === 國立成功大學 === 光電科學與工程研究所 === 95 === This thesis presents the implementation of high-linearity, low-voltage CMOS Mixer at 5.8 GHz in TSMC standard 0.18um CMOS process. A novel frequency doubler and a miniaturized broadband hybrid ring by using WIN and Transcom InGaAs PHEMT process, respectively,...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/97893051048244571238 |