A 5-bit 1-GSample/s Two-Stage A/D Converter with a New Flash Folded Architecture

• Main Authors: Hung-Yu Huang, 黃宏裕
• Other Authors: Soon-Jyh Chang
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/36816546608398772512

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 95 === For multi-band OFDM UWB applications, we propose a new architecture, which combines the characteristics of flash and folding structures, for low-power high-speed analog-to-digital conversion. The analog front-end of the proposed design is the same as that of a typical flash A/D converter. By replacing folding amplifier with current-mode multiplexer (MUX), cyclic thermometer output codes, the digital output codes of a conventional folding A/D converter, can be obtained. By manipulating this arrangement, the frequency multiplication problem of a traditional folding amplifier is alleviated. Using the proposed architecture, the number of the comparators is reduced to 16, and it is 32 for a typical flash A/D converter. A 5-bit 1-Gsample/s A/D converter is designed in TSMC 0.18-�慆 1P6M CMOS process. Operating at 1-GSample/s, the ENOB is 4.25 bits at input frequency 500 MHz. The maximum DNL is no more than 0.175 LSB and the maximum INL is less than 0.261 LSB. This A/D converter consumes 69 mW from a 1.8 V supply voltage, achieving an FOM of 2.23 pJ/ conversion-step at 1-GSample/s.