Design of Low Power Fully Parallel Binary and Ternary Content Addressable Memories

• Main Authors: Palanichamy Manikandan, 麥肯德
• Other Authors: Bin-Da Liu
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/31077159041841274519

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 95 === This thesis presents a novel VLSI architecture for fully parallel static type binary and ternary content addressable memories (BCAM and TCAM) with low power and high flexibility features by using novel CAM cell structures. The proposed CAM core cell structures eliminate the drawbacks and adapt the advantages of single bit line and dual bit line cell structures. In this work, the word match line (ML) structure of low power BCAM and TCAM adapts the proposed NAND based static pseudo CMOS (NPC) logic and static pseudo CMOS (PC) logic respectively which comprises the advantages of NAND structure such as low static power, pseudo NMOS logic such as high speed operation and CMOS logic such as low power and low cost. HSPICE simulations for 128×32 BCAM systems were performed with 0.18 �慆 technology and the result shows that the proposed design provides the power dissipation of 3.94 mW with the delay time of 2.02 ns under 1.8 V supply voltage. The measurement results of 128×32 PC-BCAM (under 0.18 �慆 CMOS technology) shows that the proposed BCAM cell reduces 76% of power dissipation and improves 65% of search speed. Further more, spice simulations were carried out for 64×128 TCAM systems with advanced local search line control (LSC) technique under 0.13 �慆 technology which shows that the proposed design gives the power dissipation of 2.04mw with the delay time of 6.06 ns under 1.2 V supply voltage. In 64×128 TCAM, proposed TCAM cell reduces 26% of power dissipation and improves about 23% of search speed.