Built-In Self Diagnosis of Pipelined A/D Converters

• Main Authors: Cho-Fan Chen, 陳卓凡
• Other Authors: Soon-Jyh Chang
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/83927857838766068751

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 95 === The main purpose of this thesis focuses on the design and diagnosis of a 50 MHz 8-bit pipelined ADC. The supply voltage of this ADC is 3.3 V and the output voltage range of each pipelined stage is from 1.15 V to 2.15 V. In the proposed Built-In Self Diagnosis circuit, we design a Stage-Under-Test Holder (SUT-Holder) to hold the output voltage of the selected pipelined stage. Then, the analog voltage of SUT is transformed into digital code by a voltage controlled oscillator (VCO) and a counter. By using the obtained digital codes to represent corresponding voltages of the pipelined stage, we can use simple digital circuits to diagnose errors in the pipelined stage. To verify this architecture, we inject faults of capacitor mismatch into SUTs to demonstrate the effectiveness of the proposed diagnosis scheme. Except the VCO, all the employed building blocks of the diagnosis scheme are digital circuits in this work. Generally, design of analog circuits with high resolution is very difficult under low supply voltage. The proposed diagnosis circuit is mostly accomplished with digital circuits. So, it is much easier to achieve higher resolution than using pure analog circuits. The offsets induced by the SUT-Holder can be cancelled in the proposed diagnosis circuit. Also, the performance degradation of the ADC caused by the added circuits is very small. All circuit designs and simulations are based on TSMC 0.35�慆 2P4M process model.