Investigation of Strained-Si NMOSFETs on SiGe Virtual Substrate with Chemical-Mechanical-Polishing Technique

• Main Authors: Hau-Yu Lin, 林浩宇
• Other Authors: San-Lein Wu
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/57646564998412038992

碩士 === 國立成功大學 === 微電子工程研究所碩博士班 === 95 === 　　In this thesis, the　strained-Si NMOSFETs structures are fabricated on the SiGe virtual substrate. Introduction of tensile strained-Si layer into Si-based structures is attributed to the fact that electron mobility can be enhanced due to energy band splitting and the reduction of effective mass. However, conventional SiGe virtual substrate usually accompanies the threading dislocation and the roughness of SiO2/Si interface. By utilizing the Chemical Mechanical Polishing technique (CMP), lower threading dislocation density and less interface roughness between SiO2 and Si are obtained. Consequently, DC performance has further been improved. 　　Additionally, roughness and the defect at interface between the channel and gate oxide generated by threading dislocation make the flicker noise performance worse. At the same way, observing the improvement of flicker noise property is also to prove the superiority of the application of CMP.