| Summary: | 碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 95 === The complexity of hardware development becomes extremely high due to the rapid progress of VLSI design tools and the demanding of highly complex systems. New design flows are needed for designers to keep up with the new trend, since it’s difficult to carry out huge designs with traditional skills. In recent years, electronic system level (ESL) design has become one of the hottest topics. ESL describes a System-on-chip (SOC) design in the more abstract way and this makes faster system simulation while providing virtual prototypes (or models) for hardware and software co-design/co-verification. It is becoming a fundamental part of overall design flow. Furthermore, incremental (or iterative) design process can be applied to cover different design levels in the same design phase, rather than just in the architecture level and/or algorithm level.
There are many issues focusing on ESL development. In this thesis, we focus on the communication problems in the so-called Transactional Level Modeling (TLM) area. In the past, designers need to take care of both computation units and communication units at the same time. Here, we develop some useful development and interface tools so that the communication problems among computation models are reduced. We provide a centralized system development platform to manage the transaction in TLM. This platform allows designers to use tools such as FPGA, Matlab and Realview SOC Designers to perform simulation of the system if some models are available in other tools only. Furthermore, one can use multiple computers, each running certain number of models, to work together across internet for remote co-simulation. Hence, engineers could focus on their own modules to make the implementation easier, faster, and more reliable. Finally, we suggest that a new design flow which includes models implemented in different abstraction level to be considered together at the same time to make the design process easier.
|
|---|
