| Summary: | 碩士 === 中興大學 === 電機工程學系所 === 95 === In this thesis, the main purpose is to realize a LO signal with multi-channels frequency synthesizer for IEEE 802.11 a/b/g. On the instant, the loop filter in the frequency synthesizer is almost combined with the resisters and the capacitors. But, the VCO’s controlled voltage is produced by loop filter and occurs the effect of ripple. This effect will generate reference spur in the spectra, and affect the performance of transmitter. For this reason, if we displace the resistor in the loop filter, it can suppress the effect of ripple in the VCO’s controlled voltage. And then, the reference spur is decreased. So, we use the fundamental architecture of the no resistor frequency synthesizer to make some improvement in this thesis. In fractional part, phase-compensation fractional PLL is a different kind of true fractional PLL with averaging fractional PLL using D-S modulator architecture. This technique can minimum generating of quantization error which makes fractional spurs. The focus of the technique is how to generate the phase for compensation.
The work presents the frequency synthesizer based on PLLs. It divided into two parts of the work. The first one applies the inductive varactor voltage-controlled oscillator and delta-sigma modulator to realize a ripple-suppressed fractional-N frequency synthesizer. The output frequency range is from 4.6GHz to 6.5GHz. It is simulated by TSMC 0.18-um standard CMOS technology and power dissipation is about 75-mW under 1.8-V supply voltage. The chip area is 1.4*1.4mm2. The other one is to realized the spur-eliminated topology base on the last architecture of frequency synthesizer. Taking advantage of multi-phase generated by a ring oscillator, it adopts with a phase generator and a phase selector which generates phase compensation to reduce fractional spur. Because of the high speed operating, the ring oscillator is accepted with dual delayed loop technique. The output frequency range is from 2.3GHz to 2.6GHz. It is fabricated with a 0.18-um standard CMOS technology and power dissipation is about 65-mW under 1.8-V supply voltage. The chip area is 0.815*0.66mm2.
|
|---|
