| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 95 === The DVB-T system is similar to most of the prior digital communication systems. It is roughly divided into two major parts, one for channel coding/decoding, and the other for modulation/demodulation. In this thesis, an implementation of a baseband receiver for DVB-T systems is presented. The receiver includes FFT, deinterleavers, FECs, and descrambler. We utilize Matlab to establish a software system-level simulation environment and use this system simulation model to evaluate performance. Furthermore, we implement total system with Verilog HDL. The design process such as Verilog HDL programming, functional simulation, place and route, timing simulation and device programming are completed with Xilinx ISE 7.1i and ModelSim SE 6.0d. The circuit was implemented with the Xilinx Virtex-4 XC4VLX100-10FF1148C Field-Programmable Gate Array (FPGA) device on Xilinx HW-AFX-FF1148-400 proto board.
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