Design of Variable Trace Width Inductor and Dual-Gate CMOS Transistor
碩士 === 國立中興大學 === 電機工程學系所 === 95 === This thesis includes two parts. The first part studies on layout design algorithm of variable widths inductor to achieve minimum metal resistance. In this work, the proposed algorithm can rapidly find the optimal width by keeping identical inductance and chip are...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33557366698144987100 |