Design of Variable Trace Width Inductor and Dual-Gate CMOS Transistor

• Main Authors: Kai-Yuen Chan, 詹凱淵
• Other Authors: 許恆銘
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/33557366698144987100

碩士 === 國立中興大學 === 電機工程學系所 === 95 === This thesis includes two parts. The first part studies on layout design algorithm of variable widths inductor to achieve minimum metal resistance. In this work, the proposed algorithm can rapidly find the optimal width by keeping identical inductance and chip area. The proposed inductors are fabricated by the foundry 90nm CMOS technology. Measurement results express that the variable width inductor improves the metal resistance and increases the quality factor of inductors. Furthermore, the variable width inductor includes the different outer dimension, turn numbers and geometry shape with identical inductances are compared in this work. Discuss the self-resonance frequency and quality factor effect in these inductors. Moreover, the investigation on dummy Metal pattern inserted under neath of on-chip inductor influences the performance. On the basis of measurement result, an equivalent model is proposed to analyze the phenomenon of Q value degradation in high frequency. Finally, an inductor with variable metal space between coils is proposed to improve the Q value. Variable space inductor not only improves the quality factor but also increases the self-resonant frequency. The second part demonstrates that the cascode configuration of Dual-Gate MOSFET and compares the difference between conventional single gate MOS transistor. Keeping the identical bias condition, the high frequency performance of Dual Gate MOSFET is compared. Measurement results show that Dual Gate MOSFET has high cut-off frequency and excellent maximum oscillation frequency. Sweeping various bias conditions, the figure-of-merit of Dual Gate MOSFET is investigated deeply. Therefore, the Dual Gate FET can be widely applied in RF circuit design.