A Metrology to Explore Collar TEOS Integrity of Deep-Submicron DT DRAM Capacitor with a Vertical Parasitic NMOSFET

• Main Authors: Ming-Hsien Weng, 翁銘賢
• Other Authors: Mu-Chun Wang
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/49262179321064969887

碩士 === 明新科技大學 === 電子工程研究所 === 95 === In this thesis, we propose an adequate measurement metrology to nondestructively verify the integrity of dielectric gap-fill in a deep trench (DT) capacitor of deep-submicron DRAM product. Because of the geometric structure in the DT capacitor, the vertical cylindrical electrode isolator similarly provides a parasitic nMOSFET. The drain terminal of this parasitic nMOSFET connects with the gate terminal, the common C-V measurement and Charge pumping measurement can not measure the integrity of the collar TEOS. There are Cell nMOSFETs near this parasitic nMOSFET, and the doping profile in these devices are very similar. Through the electrical measurement, people can analyze these drain-to-source electrical characteristics. We can find that the normalization of IDS vs. VDS trend chart of this parasitic nMOSFET is similar with that in Cell nMOSFET’s. Then, the Cell nMOSFET’s electrical characteristics are as reference for this parasitic nMOSFET. Some of most valuable device parameters, such as threshold voltage (Vt) and mobility (�愯), correlate to the interface integrity and the surface roughness between silicon substrate and gap-fill oxide (or liner oxide). Furthermore, we compared with the device parameters of peripheral n/pMOSFET and those of the parasitic nMOSFET, discussing the variation of parameters in different temperatures and channel lengthes. In other words, as these values are obtained, the degradation level of this interface or gap-fill quality can be clarified. Indirectly, the charge storage quality of this capacitor, avoiding the leakage path, can be improved with the process modification.