The FPGA Implementation Based on the Amplitude-Locked Loop Model
碩士 === 國立高雄應用科技大學 === 電子與資訊工程研究所碩士班 === 95 === Abstract In this thesis, we developed the field-programmable gate array (FPGA) based on the amplitude-lock loop (ALL) separation model. We adopted the MATLAB/Simulink and Xilinx System Generator (XSG) for the co-channel FM separated design system. The s...
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| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/13993991183591333310 |