FPGA-Based High Area Efficient Time-To-Digital IP Design with pico-second resolution
碩士 === 崑山科技大學 === 電子工程研究所 === 95 === This paper proposes a novel design for a highly area efficient FPGA-based TDC (Time to Digital Converter) IP (Intelligent Property) with resolution less than 30ps. To avoid the unpredictable internal place and route (P&R) delay, a modified ring oscillator is...
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| Format: | Others |
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2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/73994657889593537981 |