| Summary: | 碩士 === 輔仁大學 === 電子工程學系 === 95 === In today’s deep sub-micron technology era, the density and capacity of the system-on-a-chip (SOC) is increasing significantly. Moreover, embedded memories usually occupy the greatest part of the SOC. The yield of the embedded memories will dominate the SOC yield. Based on these reasons, methodologies for yield improvement of embedded memory are becoming the most important issues for the designer and manufacturer. A novel Built-In Self-Repair (BISR) scheme with global-block-based redundancy architectures is proposed in this thesis. The redundant rows/columns are divided into row/column blocks. Therefore, the repair of faulty memory cells can be performed at the row/column block level. Moreover, the redundant row/column blocks can be used to replace faulty cells anywhere in the memory array. This global characteristic is helpful for repairing cluster faults. The proposed redundancy architecture can be easily integrated with the embedded memory cores. Based on the proposed global redundant architecture, a heuristic MESP (modified essential spare pivoting) algorithm suitable for built-in implementation is also proposed. According to experimental results, the hardware overhead for implementing the MESP algorithm is almost negligible. Due to the efficient usage of the redundancy, the manufacturing yield, repair rate, and reliability can all be improved significantly.
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