| Summary: | 碩士 === 逢甲大學 === 產業研發碩士班 === 95 === With the increasing data transfer demands on wireless communication, the issues of the low-cost and high-level integration are the current for the implementation of communication system. With CMOS technology is showing the potential to meet these requirements. Due to the use of transmission line (TL), it is not practical to integrate the microwave power dividers monolithically. Though the miniaturized chip size can be achieved, they still suffer from the use a huge chip area and increasing prime cost. Therefore, the lumped-element replacement has been proposed to reduce the chip size. The bandwidth not enough is a problem, that organize component to from equivalent-elements. In this thesis, Complementary-Conducting-Strip (CCS) TLs are employed to substitute the microstrip lines, use meandered and wound to compact layout, provide microstrip lines performance and miniaturization chip area. Based on this concept, the Wilkinson power divider (WPD) is implemented in the standard 0.18 μm CMOS process for monolithic microwave integrated circuit (MMIC) applications, the CCS equivalent model to design and analysis.
By employing CCS TLs in the synthetic transmission line architecture, the WPD exhibits a wide impedance control range, compact layout and miniaturization chip area. To extract CCS unit cell parameter from the 10 x 10 CCS meander line, to simulation about to WPD from cascaded CCS unit cell. Characterized by the S-parameter simulation, the circuit demonstrates a coupling loss less than -5.51 dB and a return loss better than -13 dB with power divider at the center frequency of 11 GHz while maintaining isolation better than -15 dB from 9.3 GHz to 16.1 GHz. The occupying area of the miniaturization WPD, not including the input/output (I/O) PADs area, is 405 μm x 330 μm.
For the design of a rather compact WPD is implemented using CMOS 0.18 μm process. The fabricated circuit exhibits a coupling loss less than -4.89 dB and a return loss better than -15 dB at the center frequency of 11 GHz while maintaining good isolation between the output ports. The occupying area of the miniaturized WPD, not including the I/O PADs area, is 345 μm x 360 μm, which is suitable for the system in MMIC applications.
In this thesis, a miniaturization WPD for 11 GHz is proposed. In the first half of this thesis, theory of WPD and configurations of the CCS are described. With a compact WPD base on commercial CMOS 0.18 μm process technology is implemented and measured.
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