Simulation and Test of the Thermal Fatigue Life of an Electronic Package

• Main Authors: Chih-ming Hsu, 徐志銘
• Other Authors: Yu-chun Chia
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/83583922283927175014

碩士 === 逢甲大學 === 航太與系統工程所 === 95 === The study focuses on the reliability of wafer level chip scale package (WLCSP) subjected to cyclic temperature. The finite element analysis (FEA) is used to simulate its thermal condition and the mechanical behavior. According to the theory of an energy-based law proposed by Darveaux, the analysis adopts viscoplastic strain energy density as the criteria basis of fatigue life to calculate the package’s fatigue life that is considered as the reliability of the whole package. The package is analyzed using a whole model in ANSYS to simulate the applied thermal cycles. The results reveal that the fatigue failure is caused by the difference of CTE (Coefficient of Thermal Expansion) of components. As such, the maximum equivalent stress and strain of solder bumps always occurs around a corner in the model, where the fatigue failure is initiated. Also, similar analysis is carried out for a flip chip sample. The veracity of the simulation is shown by comparison with experiments reported by Solectron, a industrial company in USA.