| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 95 === As the complexity and speed of circuits increase, power consumption has become an important design issue. The finite state machine decomposition, which divides the original FSM into several sub-machines, had been proven an effective technique to reduce the power consumption of the FSM. Whenever the FSM performs computation, only one of the sub-machines is activated while other sub-machines have no input transitions, and thereby the power consumption can be effectively reduced due to the decrease of switching activities. Up to now, existing researches only attempt to apply FSM decomposition technique to reduce average power. In this thesis, we propose an FSM decomposition architecture which can reduce the average power and peak power of the circuit at the same time. Experimental data show that our approach works well in practice.
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