Design a MIPS ISA Processor with Compatible Interrupt Mode by using FSM-Based Methodology
碩士 === 中原大學 === 資訊工程研究所 === 95 === With the rapid growth in technology, designers create the high performance, low power and small area products by innovating the architecture and improving the process technology. In the traditional processor design, designers usually increase the pipeline stages or...
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | zh-TW |
Published: |
2007
|
Online Access: | http://ndltd.ncl.edu.tw/handle/65360920649233144754 |
id |
ndltd-TW-095CYCU5392034 |
---|---|
record_format |
oai_dc |
spelling |
ndltd-TW-095CYCU53920342015-10-13T13:56:24Z http://ndltd.ncl.edu.tw/handle/65360920649233144754 Design a MIPS ISA Processor with Compatible Interrupt Mode by using FSM-Based Methodology 以有限狀態機為基礎設計具有相容中斷模式之MIPS32指令集處理器 Chien-Pang Lai 賴建邦 碩士 中原大學 資訊工程研究所 95 With the rapid growth in technology, designers create the high performance, low power and small area products by innovating the architecture and improving the process technology. In the traditional processor design, designers usually increase the pipeline stages or enlarge instruction parallel parallelism to improve the processor performance. Different from traditional design, we make most effort to handle the complex control signals of modern processor. Therefore, in this thesis, we design a MIPS32 ISA processor and design a control unit in this processor by using finite state machine methodology. In order to make the processor more integrity, a system control processor, called Coprocessor 0, was attachs to the processor to deal with interrupts and excaptions. In this thesis, we adopt ModelSim, Debussy and nLint to check the syntax error and verify the functional correction. Than we proceed to the FPGA functional verification in the software and hardware coverification environment by using simulation model and ARM Integrator. Finally, we use a synthesis tool, Design Compiler, to synthesize tho processor under TSMC 0.13μm technology, and get the results of performance, power and area. Finally we compare the results of three processors, MIPS32 ISA processor with finite state machine, a MIPS R2000 processor and a traditional MIPS32 processor. Compare to MIPS R2000, we can observe that our design can reduce 12% power consumption and decrease the use of area by 7%. Compare the traditional MIPS32 ISA processor, we observe that the proposed processor reduce 33% power consumption and decrease the use of area by 35%. Accordly, our MIPS32 ISA processor with finite state machine can efficient achieves the target of small area and low power. Slo-Li Chu 朱守禮 2007 學位論文 ; thesis 92 zh-TW |
collection |
NDLTD |
language |
zh-TW |
format |
Others
|
sources |
NDLTD |
description |
碩士 === 中原大學 === 資訊工程研究所 === 95 === With the rapid growth in technology, designers create the high performance, low power and small area products by innovating the architecture and improving the process technology. In the traditional processor design, designers usually increase the pipeline stages or enlarge instruction parallel parallelism to improve the processor performance. Different from traditional design, we make most effort to handle the complex control signals of modern processor. Therefore, in this thesis, we design a MIPS32 ISA processor and design a control unit in this processor by using finite state machine methodology. In order to make the processor more integrity, a system control processor, called Coprocessor 0, was attachs to the processor to deal with interrupts and excaptions.
In this thesis, we adopt ModelSim, Debussy and nLint to check the syntax error and verify the functional correction. Than we proceed to the FPGA functional verification in the software and hardware coverification environment by using simulation model and ARM Integrator. Finally, we use a synthesis tool, Design Compiler, to synthesize tho processor under TSMC 0.13μm technology, and get the results of performance, power and area.
Finally we compare the results of three processors, MIPS32 ISA processor with finite state machine, a MIPS R2000 processor and a traditional MIPS32 processor. Compare to MIPS R2000, we can observe that our design can reduce 12% power consumption and decrease the use of area by 7%. Compare the traditional MIPS32 ISA processor, we observe that the proposed processor reduce 33% power consumption and decrease the use of area by 35%. Accordly, our MIPS32 ISA processor with finite state machine can efficient achieves the target of small area and low power.
|
author2 |
Slo-Li Chu |
author_facet |
Slo-Li Chu Chien-Pang Lai 賴建邦 |
author |
Chien-Pang Lai 賴建邦 |
spellingShingle |
Chien-Pang Lai 賴建邦 Design a MIPS ISA Processor with Compatible Interrupt Mode by using FSM-Based Methodology |
author_sort |
Chien-Pang Lai |
title |
Design a MIPS ISA Processor with Compatible Interrupt Mode by using FSM-Based Methodology |
title_short |
Design a MIPS ISA Processor with Compatible Interrupt Mode by using FSM-Based Methodology |
title_full |
Design a MIPS ISA Processor with Compatible Interrupt Mode by using FSM-Based Methodology |
title_fullStr |
Design a MIPS ISA Processor with Compatible Interrupt Mode by using FSM-Based Methodology |
title_full_unstemmed |
Design a MIPS ISA Processor with Compatible Interrupt Mode by using FSM-Based Methodology |
title_sort |
design a mips isa processor with compatible interrupt mode by using fsm-based methodology |
publishDate |
2007 |
url |
http://ndltd.ncl.edu.tw/handle/65360920649233144754 |
work_keys_str_mv |
AT chienpanglai designamipsisaprocessorwithcompatibleinterruptmodebyusingfsmbasedmethodology AT làijiànbāng designamipsisaprocessorwithcompatibleinterruptmodebyusingfsmbasedmethodology AT chienpanglai yǐyǒuxiànzhuàngtàijīwèijīchǔshèjìjùyǒuxiāngróngzhōngduànmóshìzhīmips32zhǐlìngjíchùlǐqì AT làijiànbāng yǐyǒuxiànzhuàngtàijīwèijīchǔshèjìjùyǒuxiāngróngzhōngduànmóshìzhīmips32zhǐlìngjíchùlǐqì |
_version_ |
1717745879061889024 |