| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 95 === With the rapid growth in technology, designers create the high performance, low power and small area products by innovating the architecture and improving the process technology. In the traditional processor design, designers usually increase the pipeline stages or enlarge instruction parallel parallelism to improve the processor performance. Different from traditional design, we make most effort to handle the complex control signals of modern processor. Therefore, in this thesis, we design a MIPS32 ISA processor and design a control unit in this processor by using finite state machine methodology. In order to make the processor more integrity, a system control processor, called Coprocessor 0, was attachs to the processor to deal with interrupts and excaptions.
In this thesis, we adopt ModelSim, Debussy and nLint to check the syntax error and verify the functional correction. Than we proceed to the FPGA functional verification in the software and hardware coverification environment by using simulation model and ARM Integrator. Finally, we use a synthesis tool, Design Compiler, to synthesize tho processor under TSMC 0.13μm technology, and get the results of performance, power and area.
Finally we compare the results of three processors, MIPS32 ISA processor with finite state machine, a MIPS R2000 processor and a traditional MIPS32 processor. Compare to MIPS R2000, we can observe that our design can reduce 12% power consumption and decrease the use of area by 7%. Compare the traditional MIPS32 ISA processor, we observe that the proposed processor reduce 33% power consumption and decrease the use of area by 35%. Accordly, our MIPS32 ISA processor with finite state machine can efficient achieves the target of small area and low power.
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