A design of Analog-to-Digital Converter for IEEE 802.11a WLAN system
碩士 === 中華大學 === 電機工程學系(所) === 95 === This paper proposes a 10-bit, 40MS/s CMOS pipelined analog-to-digital converter (ADC) which applied to IEEE 802.11a Wireless LAN (WLAN) communication system. We discuss the structures and components of the proposed pipelined ADC operating at a 3.3V supply voltage...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/98392786387006611954 |
| Summary: | 碩士 === 中華大學 === 電機工程學系(所) === 95 === This paper proposes a 10-bit, 40MS/s CMOS pipelined analog-to-digital converter (ADC) which applied to IEEE 802.11a Wireless LAN (WLAN) communication system. We discuss the structures and components of the proposed pipelined ADC operating at a 3.3V supply voltage which is implemented in TSMC 0.18μm CMOS process. Owing to using Switched-capacitor Common Mode Feedback and Digital-Error-Correction technique, we design this ADC by using less-sensitive fully-differential dynamic comparator. The great merits are no static power consumption and better noise-immunity. Operational Transduction Amplifier (OTA) consumes only 7mW. The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.34 dB with a full-scale sinusoidal input at 1MHz.
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