Automatic Fault Tolerance Insertion Using Direct Graph Modeling for High Level Language Description

• Main Authors: Li-Wen Lin, 林立文
• Other Authors: Yung-Yuan Chen
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/48060704065084284254

碩士 === 中華大學 === 資訊工程學系碩士班 === 95 === Designers who want to construct a reliable system crave the “Fault Tolerant Design Automation (FTDA)” so that they even dreams about it. They wish to generate a fault tolerant system only by setting several parameters to a tool and don’t need to consider problems such like how to analysis a system and modify it, etc. However, fault tolerant design must bring additional hardware overhead, performance degradation and power dissipation because the major difference of reliable and un-reliable systems is that the prior require providing the protecting mechanism for enhancing the tolerant capability of faults. Because designers commonly lake for related knowledge and developing experiments so that they can’t choose an appropriate fault tolerant technique and apply it to a system. That’s another main reason why they need a FTDA tool. In a traditional fault tolerant design process, the obtainment of data used to judge the robustness of a system relies on the analysis of simulating results. This is not a simple job, also the modification of design. Both of them lead to the arrearage of FTDA tool. In this thesis, we don’t investigate the analysis of system but focus on the modification from an un-reliable system to a reliable one. Based on the VHDL platform, we provide various protecting scheme which can be chosen for appending to the arithmetic and logical operators automatically so that we can improve the reliability of a system.