24GHz Low Power Receiver Design

• Main Authors: Chen-Yuan Chu, 朱振源
• Other Authors: Wu-Shiung Feng
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/44839130616291140101

碩士 === 長庚大學 === 電子工程研究所 === 95 === Abstract This thesis presents the development of 24GHz RF front-end circuit for indoor wireless application. The study is to integrate the transceiver circuit into a single chip to benefit the integration of the base-band circuit and to realize the manufacture of SoC (System on a Chip). For the demands of indoor wireless application, the CMOS RF receiver is focused on low power consumption, and operated at 24GHz to raise transmission rate. The CMOS RFICs include low noise amplifier, down conversion mixer, voltage-controlled oscillator and variable gain amplifiers. Planning the arrangement of the system, the RF frequency is 24GHz. The base-band frequency is 100MHz. In this thesis, low noise amplifier has a gain of 14dB and noise figure is smaller than 4.9dB. Input and output return losses are smaller than -11.9dB and -13dB, respectively. Power consumption is 7.9mW. Down conversion mixer has a conversion gain of 8.5dB and double-sideband noise figure is smaller than 5.6dB. Return loss of RF Port is smaller than -14.3dB. Power consumption is 15.8mW. VCO operates around 23.5GHz to 24.4GHz with –106.9dBc/Hz@1MHz phase noise, tuning range of 950MHz, output power of –6dBm, and power consumption of 7.8mW. The RF front-end simulated performances of the topology are conversion gain of 23.3dBm, noise figure of 5.32dB, 1dB of -27dBm and IIP3 of -17.4dBm. Finally the output voltage margin of base-band single amplified by VGA is 1.8V. VGA has a voltage gain of 31dB. The total power consumption of RF front-end circuit is just 33.65mW. The circuits are simulated by Advanced Design System (ADS) and TSMC 0.18µm 1P6M CMOS process.