Design of an Asynchronous Cache Controller
碩士 === 長庚大學 === 電機工程研究所 === 95 === Cache is a kind of random access memory (RAM), whose access time is shorter than the general RAM. When the central processing unit (CPU) needs data, it will search the cache first. If the data is temporarily stored herein while read before, it would not be necessar...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/26752713443890059552 |