A High-Performance Low-Power Multiplier with Reduced Spurious Switching
碩士 === 國立中正大學 === 電機工程所 === 95 === Electronic portable devices, such as cellular phones, PDA, and digital camera, are commonly used in recent year. Digital signal processors (DSP) are often applied on these electronic apparatus. How to minimize power consumption without losing speed performance is v...
Main Authors: | Tsung-Han Yang, 楊宗翰 |
---|---|
Other Authors: | Jinn-Shyan Wang |
Format: | Others |
Language: | zh-TW |
Published: |
2007
|
Online Access: | http://ndltd.ncl.edu.tw/handle/12811193786383626944 |
Similar Items
-
Reduction of Spurious Signal Upconversion in Frequency Multipliers
by: Zenon Szczepaniak, et al.
Published: (2020-07-01) -
A High-Performance and Low Power Montgomery Multiplier for RSA Cryptosystems
by: 許恩
Published: (2003) -
Glitch Minimization on a SIMD Multiplier
by: Tsung-Han Tsai, et al.
Published: (2008) -
High-Speed and Low-Power SIMD Multipliers
by: Yuan-Ting Fu, et al. -
High-Speed and Low-Power SIMD Multipliers
by: Yuan-Ting Fu, et al.
Published: (2005)