A High-Performance Low-Power Multiplier with Reduced Spurious Switching
碩士 === 國立中正大學 === 電機工程所 === 95 === Electronic portable devices, such as cellular phones, PDA, and digital camera, are commonly used in recent year. Digital signal processors (DSP) are often applied on these electronic apparatus. How to minimize power consumption without losing speed performance is v...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/12811193786383626944 |
| Summary: | 碩士 === 國立中正大學 === 電機工程所 === 95 === Electronic portable devices, such as cellular phones, PDA, and digital camera, are commonly used in recent year. Digital signal processors (DSP) are often applied on these electronic apparatus. How to minimize power consumption without losing speed performance is very important. Multiplier plays the most important role on DSP, since it usually organizes the critical path of DSP. The low power and high speed characteristics of multiplier become more and more important. Decreasing glitches is a suitable method to reduce the power consumption while the speed performance is not sacrificed. We propose a new Modified Booth Encoding and a tree architecture to reduce glitches in the Multiplier.
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