Reconfigurable hardware platform for high-efficiency video computing

• Main Authors: Li-Hsun Chen, 陳立勳
• Other Authors: Oscal T.-C. Chen
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/64259058487641801876

博士 === 國立中正大學 === 電機工程所 === 95 === The development of digital home allows various electronic devices working together to realize services of home automatic, multimedia entertainment, digital learning, health care and so on. This trend demands that an electronic device is designed to support multiple information-processing standards. Particularly in high computational complexity of video codecs, effectively processing multi-standard video codecs has become the critical issue that need be addressed in this electronic device. In addition to the use of the Application-Specific Integrated Circuit (ASIC) and Digital Signal Processor (DSP), the reconfigurable hardware platform can be used to offer a solution to realize video codecs. Considering computational performance and computational flexibility, the reconfigurable hardware platform is very suitable to realize the multi-standard video codecs. In this dissertation, a reconfigurable hardware platform is proposed to include a reconfigurable unit and an adaptive data path designed by the proposed bottom-up and top-down approaches, respectively. By using the bottom-up approach, the reconfigurable unit can allow the hardware recourses to be fully utilized in processing video data, achieving high hardware efficiency. For the adaptive data path realized by the top-down approach, it is built based on the data path of the conventional DSP, to increase flexibility of data delivery by employing the reconfigurable methodology. Such design enables the hardware resources in the computational units to be used in maximum for data processing. Comparing to the data path of the TI TMS320C64x DSP, the proposed adaptive data path can reduce 23.10% and 28.43% of clock cycles to conduct the low-level functions of MPEG-2 video encoder and H.264 video decoder, respectively. Usually, the Multiplication-Accumulation Computation (MAC) unit is adopted in DSP. Hence, an MAC architecture with minimizing switching activities of its circuits was also developed, and can be utilized in the proposed reconfigurable hardware platforms, lowering power consumption. From the simulation results, the proposed MAC unit consumes less power than the conventional ones by at least 9.87%. As well as multi-standard video codec computing, the design methodology used for the proposed reconfigurable platform can be extended to realize the other multiple standards in one platform, achieving low hardware complexity, low power dissipation and high computational efficiency.