Implementation of MPLS Router Data Plane with QoS Guarantee and Fast Re-Route Support on High Performance Network Processor Based Platform
碩士 === 國立中正大學 === 電機工程所 === 95 === MPLS (Multi-Protocol Label Switching) is an emerging switching technology on packet-switched networks. It adopts the concept of Virtual Circuit which was introduced by ATM (Asynchronous Transfer Mode) to provide fast packet switching services. Since MPLS combines t...
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| Format: | Others |
| Language: | zh-TW |
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2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/32343015713760710334 |
| Summary: | 碩士 === 國立中正大學 === 電機工程所 === 95 === MPLS (Multi-Protocol Label Switching) is an emerging switching technology on packet-switched networks. It adopts the concept of Virtual Circuit which was introduced by ATM (Asynchronous Transfer Mode) to provide fast packet switching services. Since MPLS combines the advantages of both connection-oriented and packet-switching, it is recommended to deploy QoS (Quality of Services) guaranteed and TE (Traffic Engineering) featured network infrastructure over MPLS. Networks with MPLS-TE support have better resource utilization and higher overall throughput. Moreover, higher service survivability can be achieved by using fast failure recovery technologies such as FRR (Fast Re-Route). DiffServ (Differentiated Services) is an architecture which uses several technologies based on the per-class basis trying to provide scalable QoS guarantee with low complexity on the Internet. Network Processor is a fully programmable embedded system. It delivers the power of programmability and the high performance approaching to the ASICs. In this thesis, we implement the DiffServ enabled and TE-FRR supported MPLS edge/core router data plane based on the IXA software development framework on the IXP2400 Network Processor based platform. We also provide the functionality verifications and performance evaluation through several experiments.
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