| Summary: | 碩士 === 國立中正大學 === 資訊工程所 === 95 === In embedded system, the RISC processor could support several requirements. Furthermore, a well design RISC processor that will improve the quantity of effect of processes execution. However, if we want to increase the performance of RISC processor, we have to increase frequency. The best choice is to add more pipelines for high frequency. The more pipelines will increase the quantity of design of complexity. This situation will more and more critical if we need higher frequency.
In this thesis, we support a design flow to simplify RISC processor design. That includes several kinds of problem and solution. Furthermore, we support many kinds of data to prove the correctness of analysis and implementation. Finally, we will show the performance of whole RISC architecture. That has high IPC and frequency. We are satisfied the outcome.
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