A power aware task scheduling algorithm for SMT processors

• Main Authors: Chih-tsung Chien, 簡志璁
• Other Authors: Shi-wu Lo
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/64071479067195412528

碩士 === 國立中正大學 === 資訊工程所 === 95 === Dynamic voltage scaling (DVS) AND Dynamic frequency scaling (DFS) are major power-saving scheduling algorithm in nowadays embedded system. These two algorithms emphasize on dynamic adjusting frequency and supply voltage to make good use of slack time to shorten the system idle time and improve the system performance. In this paper, since Simultaneous Multi-Threading (SMT) can improve task level parallelism efficiently, we propose one scheduling algorithm basing on this architecture. Different from DVS and DFS that low down the frequency, we try to delay task execution in proper situation to make many tasks be executed at the same time to save system’s execution time. In addition, we will adjust the frequency properly in order to prevent the miss deadline from happening. Through the simulation, we can prove that this scheduling algorithm is much better power-saving than current scheduling algorithm.