| Summary: | 碩士 === 國立中正大學 === 資訊工程所 === 95 === With the popularity of SOC, embedded processors with new technology emerged rapidly. To reduce the cost and improve performance simultaneously, all sorts of architecture have been investigated. Although architecture plays a significant role in the performance of processors, compiler is essential and crucial to it. Our proposed architecture has two cores and three register banks, and one of the register banks is shared by the two cores. The banked register file reduces the cost but results in more constraints and overhead, so that we desire to reduce the overhead by exploiting the shared register bank. Various register allocation algorithms have been proposed so far; however, none of them would perform well over all kinds of architectures. In this paper, we proposed a novel register allocation algorithm for our architecture. The algorithm takes instruction scheduling and code partitioning into consideration and adopts a heuristic analysis. To demonstrate the efficiency of our approach, we implemented it on GCC and simulated on a cycle accurate simulator. And the experimental results show that our proposed method has excellent performance improvement on average.
|
|---|
