Capture System Resource on Reconfigurable Architecture

• Main Authors: Yi-Cheng Chen, 陳奕成
• Other Authors: Chaio-Jang Hwang
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/05098633066585316981

碩士 === 元智大學 === 資訊工程學系 === 94 === In this paper we proposed a method to capture the FPGA system information for a dynamic reconfigurable architecture. We proposed this idea in order to design reconfigurable architecture easier and flexible. The FPGA system information report recorded how many logic gates were used. The kernel system can decide which sub-module is suitable for the system from the FPGA system information. In traditional reconfigurable architecture, the information of current system situation was hard to know. It was confined by the design rule of FPGA provider. In the dynamic reconfigurable architecture, there were two design modes: one was Difference Base Design (DBD) and the other was Module Base Design (MBD). When a system was designed with MBD mode, system couldn’t get correct usage information as sub-module change. If there were a lot of functions, they will be implemented. The reconfigurable architecture systems demand more free space on the FPGA. Now we proposed a method to capture the current usage information as corresponding to every sub-module. The whole system knew how many logic component had used, and selected the best sub-module. The whole the system can be improved more flexible and high performing.