| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 94 === This thesis proposed a new circuit architecture that solves the pulse-width quality problem of the high-speed digital-system-chip clock signal. From pervious studies, high-speed pulse-width control can divide into two kinds of circuit structures. Firstly, the mixed-signal pulse-width controlled loops were proposed, and it is easy to be caused locking error of the preset pulse-width by process, voltage, temperature, etc. Another kind of newest structure is all-digital pulse-width controlled loops. Though the way of all digital has already improved the mixed-signal pulse-width setting and locking error problem, its structure is only applied to single frequency in one pulse-width setting. This makes it design and use having difficulties.
This thesis proposed new circuit architecture, and solved the frequency range and pulse-width setting problem in the pulse-width locked loop. We proposed, in this thesis, a reusable pulse detector to reduce the unnecessary signal passing through in order to prevent the surplus power consumptions. Meanwhile, we have designed the extendible register for storing, detecting, and examining the pulse converter binary data produced repeatedly. Then shift and filter the binary data to calculate the cycle and pulse-width of the clock signal with new register. Finally, use mapping table to transfer the desired value which produce new pulse-width. The circuit carrying on above-mentioned movement procedure repeated, can lock pulse signal on 20% , 30% , 40% , 50% , 60% , 70% and 80% pulse-width, respectively. We finished the IC layout and the parameter extraction in TSMC 0.18-μm CMOS mixed-signal 1P6M 1.8-V technology. The post-layout simulation shows that our new architecture can work in high-speed clock frequency ranging from 400-MHz to 500-MHz, and the pulse-width can be locked from 20% to 80% duty cycle, successfully. The chip area of the main circuit is only about 277-μm × 270-μm.
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