THE DESIGN OF A DOUBLE-PATH FOURTH-ORDER BANDPASS DELTA-SIGMA MODULATOR

• Main Authors: Sung-Jr Chen, 陳頌智
• Other Authors: Shu-Chuan Huang
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/08139767426063767832

碩士 === 大同大學 === 通訊工程研究所 === 94 === The research purpose of this thesis is digital IF A/D converter. An oversampling bandpass delta-sigma modulator has been designed. Nyquist-rate A/D converters used in the conventional receiver is not suitable for digital IF receiver structure. Because IF signal is often several 10MHz, the oversampling rate will be great, and the analog circuit at a high sampling frequency is very difficult to realize with low power consumption. Therefore, the use of a bandpass delta-sigma modulator has been adopt to directly digitalize the IF signal by lower sampling frequency (usually 4 times of the center frequency). In this kind of receiver, the in-band quantization error is related to the oversampling ratio. These can reduce quantization error, and avoid non-idealities characteristic. A lot of system architectures were proposed in the literature, and prove the above advantages. Therefore, bandpass delta-sigma modulators play an important role in the digital IF receiver or possibly digital RF receiver in the future. In this thesis, a double-path fourth-order bandpass delta-sigma modulator was built based on a switched-capacitor (SC) filter with lower thermal noise and less sensitive to the capacitor mismatch. Two interleaved paths clocked at 50MHz. The effective sampling frequency is 100 MHz. A 200 kHz bandwidth signal is centered at 25 MHz. The design flow corresponding to the CAD tools is as followings. The Delta-Sigma Toolbox for MATLAB and SIMULINK are used for defining the valid building block specifications. Then, HSPICE is used for transistor-level simulations. The modulator is simulated by using the HSPICE models of TSMC 0.35μm CMOS 2P4M process. The power consumption is 55mW. The peak signal-to-noise ratio is about 70 dB.