A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits

A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits

碩士 === 淡江大學 === 電機工程學系碩士班 === 94 === Modern design and package technologies make external testing increasingly difficult and the built-in self-test (BIST) has emerged as a promising solution to the VLSI testing problem. BIST is a design for testability methodology aimed at detecting faulty component...

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Bibliographic Details
Main Authors:	Po-Han Wu, 吳柏翰
Other Authors:	Jiann-Chyi Rau
Format:	Others
Language:	en_US
Published:	2004
Online Access:	http://ndltd.ncl.edu.tw/handle/59903918325175860174

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