A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits

• Main Authors: Po-Han Wu, 吳柏翰
• Other Authors: Jiann-Chyi Rau
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/59903918325175860174

碩士 === 淡江大學 === 電機工程學系碩士班 === 94 === Modern design and package technologies make external testing increasingly difficult and the built-in self-test (BIST) has emerged as a promising solution to the VLSI testing problem. BIST is a design for testability methodology aimed at detecting faulty components in a system by incorporating test logic on-chip. The main components of a BIST scheme are the test pattern generator (TPG), the response compactor, and the signature analyzer. The test generator applies a sequence of patterns to the circuit under test (CUT), the responses are compacted into a signature by the response compactor, and the signature is compared to a fault-free reference value. During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may use longer test time and more power consumption, then it would not provide sufficiently high fault coverage and many patterns were undetected faults (useless patterns). In order to reduce the test time and power consumption in testing, we modify the scan chain architecture and use critical patterns from ATPG to improve test length and achieve high fault coverage. In this paper, we proposed a novel hardware architecture base on “LBIST Controller” to reduce test application time and test power consumption. A given test cubes with unspecified bits that generated by a sequential automatic test pattern generator (ATPG). Using the proposed algorithm in chapter 4.3 can group test cubes to several section schemes, then mapping to the proposed hardware architecture in chapter 4.1 and chapter 4.2. While “Section Counter” is more than zero, scan in could go through MUX and bypass the flip-flops in “Fixed Group”. And we can save power consumption and test application time. According to our simulation results, we reduce about 20%~60% power consumption and 50%~80% test application time in some ISCAS’89 benchmarks.