| Summary: | 碩士 === 淡江大學 === 電機工程學系碩士班 === 94 === Recent advance in TAM optimization has discussed broadly. The actual restrictions considered are more and more rigorous in their method. For example, they maybe think about the embedded core frequency or power consumption during TAM optimization. But some of the researches usually consider incomplete. It can not do the comprehensive doing in the test amount. Therefore, we take into account the optimization problem as below: first, as each core with different work frequency, we can roughly divide these cores into two sets; high and low frequency; second, each core has its own power consumption under test processes; third, the hierarchy relation does exist between each core.
In recent years the advance of CMOS technology has led to a great development, especially on the complexity of the system-on-chip (SOC). It not only increases the layout complexity but also increase the degree of difficulty. As the development of circuit with different technology, the embedded cores embedded into system-on-chips (SOCs) usually have multi-frequency to drive it. In other words, a core may work under different clock cycles. This ability was restricted by its frequency limitation. The total is come to say, all of the core’s working frequency can be divided roughly into two kinds: low-frequency and high-frequency. If we want to test a core at high-speed, we must to be transported the test data at high data rate. This work can be done by ATEs include the Agilent 93000 series tester [1]. But the speech in fact, the test channels with high data rate are constrained on the ATE resource limitations, power rating of the SOC, and scan frequency limit for the embedded cores. On these premise, optimization technique must ensure all of the constraint has already considered, such that high-frequency channels can be used reasonable during SOC test.
In this paper, we present a heuristic approach of TAM optimization according to the reality and reduce the test application time. Unlike prior methods that consider the incomplete situation, the proposed method is applicable to the real-world design model with hierarchy SOCs. We pay the price in hardware overhead in order to decrease test application time.
|
|---|
