| Summary: | 碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 94 === Due to the technology of integrated circuit progress rapidly, the number of transistors increase in a system-on-a-chip. Therefore, a FPGA (Field Programmable Gate Array) chip can contains more and more logic element components. How to verification and design in FPGA systems is a significant issue. The step of verification in system design can make sure the correctness of system function and reduce the system development time. There have several kinds of verification method from abstract level to physical level. In this thesis, we develop a FPGA system automatically functional verification tool, namely FVT (Functional Verification Tool). We use a functional verification method which can quickly verify a lot of signals among system test pattern, and the results of system simulation and emulation. In this verification tool, we propose a functional verification algorithm and a graphical user interface (GUI) to speed up the FPGA verification. When designer finished the system hardware design, then output data will be generated by system simulation and system emulation. For reducing the errors from comparison of the results of system simulation and emulation by manual, the system designer can build a system test pattern for in system specification to automatically verify the results from simulation and emulation. Finally, two verification examples, LCD (Liquid Crystal Display) module and ADPCM (Adaptive Pulse Code Modulation) module, are used to illustrate the correctness and feasibility of our proposed verification tool.
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