| Summary: | 碩士 === 國立臺北科技大學 === 電機工程系所 === 94 === In this thesis, the major study is focused on the comparison of second-order
sigma-delta modulator with switched-capacitor and switched-current techniques. We not
only discussed the system stability, but also compensated the IC’s non-ideal effect with
some mature techniques of compensation.
In a voltage mode, we use a switched-capacitor parasitic-insensitive integrator to
improve non-idealities which are produced by parasitic capacitors. In a current mode, we
use sample-and-hold circuit which consists of both a feedback circuit to reduce the
impedance at the input and a common-mode feedforward (CMFF) circuit to improve the
common-mode offset at the output.
The second-order delta-sigma modulators simulate with the parameters of the TSMC
0.35μm CMOS process technology. The SC and SI simulation results reveal that the
maximum signal to noise and distortion ratio (SNDR) is 89 dB and 86.3 dB, respectively,
within the conditions that the sampling rate is 10.24MHz, the oversampling ratio is 128,
and the power consumption is 12mW. Note that the structure, the power dissipation, and
the speed are the same.
Furthermore, we point out the differences of the sample and hold circuits between
switched-capacitor and switched-current techniques. By Hspice simulation, the system
implementation is finished with a hierarchical description.
Keywords：delta-sigma modulator, sample and hold circuit, switched-current circuit,
switched-capacitor circuit, common-mode feedforward (CMFF).
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